Résumé

Experience

1. Tenstorrent · Sr. Staff Engineer, SoC / Chiplet Design Lead

   May 2026 – Present

   SoC chiplet design lead for advanced SoC and chiplet architectures targeting AI, HPC, and automotive markets.

   • Leading the memory chiplet effort and cross-functional teams through the full SoC lifecycle, from concept and architecture through RTL, verification, and tape-out.

2. Cadence Design Systems · Sr. Design Engineering Manager / Sr. Principal Design Engineer, IP R&D

   Jun 2022 – May 2026

   Led cross-functional product development across hardware, software, DV, PD/PE, and validation for next-generation DFT IP (Modus) used by Tier-1 SoC customers.

   • Design lead for JANUS IP: a packet-based, wire-optimized, FuSa-compliant non-coherent NoC, now offered commercially as Cadence IP.
   • Architected a compiler-driven configurable RTL generation framework (Perl + Verilog), reducing development cycles by ~10%.
   • Pioneered a DFT-specific network architecture enabling automated SoC-level test distribution (in-field or ATE), including advanced-node (1.4nm) customer test-chip validation.
   • Delivered modular, partition-aware system NoC (AXI/APB/AHB) and test-infrastructure IP (LBIST/MBIST/POST/IJTAG/3DIC) for first-silicon test-chip success.
   • Architecture lead for a $1M+ program directing an external service team building an in-system test controller for hyperscaler/AI in-field ASIL-D testing.

3. Texas Instruments · Senior Digital Design Engineer / SoC Integration Lead

   Jun 2017 – Jun 2022

   Led the SoC integration team for silicon-proven 16nm AM64x SoCs, owning top-level RTL assembly and power/reset/clock/debug microarchitecture.

   • Microarchitect for clocking, debug, and power on the TDA4 (Jacinto 7) ADAS platform; integrated IP across TDA4 and AM62x (5+ SoCs), enabling cross-platform reuse.
   • 16nm PBIST memory-test IP owner and architect. Built run-time PBIST infrastructure and custom programmable BIST algorithms for ASIL-D and ASIL-B certification.
   • Architected an improved memory built-in self-repair delivering measurable yield improvement and reduced FIT rate across production devices.
   • Reduced design cycles by 10% through SoC integration flow automation; supported post-silicon debug, ECO resolution, and ATE V/F Shmoo validation through production ramp.

4. Luxima Technology · Digital Design Co-Op Engineer

   May 2016 – May 2017

   Digital blocks (ADC/LVDS driver) on CMOS image-sensor products.

   • Built an FPGA-based high-speed camera system on Virtex-7 for automated wafer defect inspection.