Varun Singh

Selected work

Four programmes that shipped, spanning interconnect, test infrastructure, and full-lifecycle SoC integration.

1. 01Cadence · 2022–26

   JANUS non-coherent NoC IP

   Design lead for a packet-based, wire-optimized, generatable, FuSa-compliant network-on-chip. Now offered commercially as Cadence IP.

   • NoC
   • ISO 26262
   • RTL generation
2. 02Cadence · 2023–26

   DFT-specific test network

   Pioneered a network architecture that distributes test across an SoC automatically, in-field or on ATE. Validated on advanced-node (1.4nm) customer test chips.

   • DFT
   • In-field test
   • 1.4nm
3. 03Texas Instruments · 2017–22

   Memory self-repair & PBIST

   Architected improved memory built-in self-repair delivering measurable yield gain and reduced FIT rate in production, plus 16nm PBIST infrastructure for ASIL-D certification.

   • MBIST
   • Yield
   • ASIL-D
4. 04Texas Instruments · 2017–22

   TDA4 & AM64x SoC integration

   Microarchitect for clocking, debug, and power on the Jacinto 7 ADAS platform; led top-level integration across 5+ automotive and industrial SoCs.

   • SoC integration
   • ADAS
   • 16nm