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Research record

Publications

Peer-reviewed work in silicon test and design.

Peer-reviewed

  • IEEE ITCUnder review

    Lead-author paper on logic built-in self-test (LBIST), submitted to the IEEE International Test Conference, the field's principal venue for electronic test.

    Details published here on acceptance.

Patents

12 granted U.S. patents across 6 invention families, with 6 further applications pending, covering memory test and repair, distributed test power control, and clocking and reset architecture.

Full patent record →

Peer review & professional service

  • IEEEMembership · 2026

    Senior Member

    Elevated by an Admission and Advancement review panel, a grade held by roughly the top ten per cent of IEEE members.

  • DATE 2027Service · 2027

    Technical Program Committee

    Architectural and microarchitectural design track at Design, Automation and Test in Europe, one of the field’s principal design-automation conferences.

Available to review for IEEE conferences and journals in test, DFT and on-chip interconnect. Programme chairs are welcome to get in touch.

Identifiers

More than one researcher publishes under this name. These resolve the record to me.