Varun Singh

I have spent a decade on the parts of a chip that no design works without: the interconnect that moves data between blocks, the infrastructure that lets a device test and repair itself, and the clocking and reset architecture that decides whether any of it reaches production and how long it lasts once it does.

I came to it through electronics and communication engineering at SRM Institute of Science and Technology, then a master’s in Electrical Engineering at theUniversity of Southern California, where digital design stopped being coursework and became the thing I wanted to do.

While still at USC I joined Luxima Technology, a startup building CMOS image sensors. It was the right kind of first job: small team, fast pace, and no distance between a design decision and its consequences. I worked on ADC and LVDS driver blocks and built an FPGA-based high-speed camera system on a Virtex-7 for automated wafer defect inspection.

Texas Instruments is where that turned into a career. I led SoC integration for silicon-proven 16nm devices and was microarchitect for clocking, debug and power on the Jacinto 7 TDA4 ADAS platform, working across the AM64x, AM62x and AM67 families. I owned the 16nm PBIST memory-test IP and architected an improved memory built-in self-repair that delivered measurable yield improvement and reduced FIT rate in production. That work became six invention families and twelve granted U.S. patents.

At Cadence I moved from building chips to building the IP other companies build chips with. I was design lead for JANUS, a packet-based, functional-safety-compliant non-coherent NoC now sold commercially, and worked on LBIST within the Modus DFT solution. I also pioneered a DFT-specific network architecture that distributes test across an SoC automatically, validated on advanced-node customer test chips down to 1.4nm.

I am now at Tenstorrent, leading the memory chiplet effort and contributing to the Grendel device programme, taking architectures from concept through to tape-out. The problems that interest me most are the ones where test, power and safety stop being separate concerns, which is increasingly where AI silicon lives.

I became a Senior Member of the IEEE in 2026, and I serve on the Technical Program Committee for DATE 2027, the Design, Automation and Test in Europe conference, on the architectural and microarchitectural design track. Reviewing other people’s work turns out to be one of the better ways to keep learning.