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Varun Singh is a Sr. Staff Engineer at Tenstorrent working on SoC and chiplet architecture, with 12 granted U.S. patents in memory test and repair.
Short biography, 50 words
Varun Singh is a digital design and design-for-test leader with over ten years across SoC integration, system IP development and test infrastructure. He has delivered five or more high-volume production SoCs and two commercial IPs, and holds 12 granted U.S. patents. He is currently SoC chiplet design lead at Tenstorrent.
Full biography
Varun Singh is a Sr. Staff Engineer and SoC chiplet design lead at Tenstorrent, where he leads the memory chiplet effort for architectures targeting AI, HPC and automotive markets.
Previously he was Sr. Design Engineering Manager in IP R&D at Cadence Design Systems, where he was design lead for JANUS, a packet-based, functional-safety-compliant non-coherent network-on-chip now offered commercially, and pioneered a DFT-specific network architecture enabling automated SoC-level test distribution, validated on advanced-node customer test chips. Before that, at Texas Instruments, he led SoC integration for silicon-proven 16nm devices and served as microarchitect for clocking, debug and power on the TDA4 ADAS platform.
He holds 12 granted U.S. patents across 6 invention families, an M.S. in Electrical Engineering from the University of Southern California, and certifications as an ISO-26262 Functional Safety Engineer and ISO/SAE 21434 Cybersecurity Engineer.
Fact sheet
- Name
- Varun Singh
- Current role
- Sr. Staff Engineer, SoC / Chiplet Design Lead
- Organisation
- Tenstorrent
- Based in
- Dallas–Fort Worth, Texas
- Granted U.S. patents
- 12
- Invention families
- 6
- Education
- M.S. EE, University of Southern California
- Contact
- varun@iamvarunsingh.com
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