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12 granted · 6 invention families · 3 pending

Patents

Twelve granted U.S. patents, grouped by invention rather than listed by number. Each family is written in plain English: what problem it addresses, what the invention does, and why it matters, because patent language is designed for examiners, not for readers.

  1. 01Memory repair

    Management of multiple memory in-field self-repair options

    The problem

    Memory cells do not only fail on the tester. They degrade over a device’s service life. A car built today is expected to run its silicon for fifteen years or more, long after any factory repair opportunity has passed.

    The invention

    Give the device more than one repair mechanism and put a test controller in charge of choosing between them, so repair decisions can be made in the field rather than fixed at manufacture.

    Why it matters

    Extends the useful life of parts already deployed, and underpins the safety case for memory that has to keep working long after it leaves the factory.

    Granted (2)

    International counterparts

    • WO 2020/205884
    • EP 3948870
    • CN 113826164
    • CN 118136085
  2. 02Memory repair · Area efficiency

    Non-volatile memory compression for memory repair

    The problem

    Repair data has to survive power cycles, so it lives in on-chip non-volatile memory or fuses, some of the most expensive area on a die. As memory content grows, the fuse budget grows with it.

    The invention

    Assign a compression parameter derived from each memory instance’s own configuration, then compress the repair code against it, so the stored footprint scales with what a given memory actually needs.

    Why it matters

    Directly reduces die area and cost on every part shipped, the kind of saving that compounds across high-volume production.

    Granted (3)

    International counterparts

    • WO 2022/133166

    Pending

    • US20250225034A1
  3. 03Memory repair · Built-in self-repair

    Built-in memory repair with repair code compression

    The problem

    Built-in self-repair has to generate repair codes, move them, and store them. If each stage assumes a different format, the design pays for the largest one everywhere.

    The invention

    Put compression logic inside the repair controller itself, so codes are encoded as they are produced and the non-volatile controller stores exactly that compact representation.

    Why it matters

    Makes self-repair practical at scale by keeping the repair path and the storage path in agreement end to end.

    Granted (3)

    International counterparts

    • WO 2022/132993
    • CN 116601712

    Pending

    • US20240321378A1
  4. 04Clocking · Reset architecture

    Technique for clock alignment supporting reset isolation

    The problem

    Modern SoCs reset one subsystem while the rest keeps running. When the isolated block rejoins, its clock can return out of phase with everything else, and the resulting corruption is intermittent and extremely hard to debug.

    The invention

    A timer derives an alignment signal from the reference clock; the clock to the affected subcircuit is blocked when it switches back, then released only on an alignment boundary, so domains resume in step.

    Why it matters

    Makes reset isolation safe to use, which is what lets a chip power down and restart parts of itself without disturbing the rest.

  5. 05Design-for-Test · Power

    Distributed mechanism for fine-grained test power control

    The problem

    Self-test switches far more of a chip at once than normal operation ever does. Run it everywhere simultaneously and you exceed the power envelope, which either damages the part or produces failures that were never real.

    The invention

    Distribute power-control circuitry per processor core alongside its BIST logic, so test activity can be throttled at fine granularity instead of gated as one monolithic block.

    Why it matters

    Lets large multi-core devices test themselves thoroughly while staying inside a safe power envelope, increasingly the limiting factor for in-field test on AI and datacenter silicon.

    Granted (1)

    International counterparts

    • EP 4198736
    • JP 2023-088881

    Pending

    • US20250123903A1
  6. 06Power management · Reset architecture

    Power-on-reset signal isolation during lower power mode

    The problem

    In low-power modes a power-on-reset can reach subsystems that were supposed to hold their state. A USB controller loses its enumeration, or a memory controller loses its training, and to the user it looks like the device simply dropped its peripherals.

    The invention

    Isolate the affected power domain (USB and memory-controller subsystems) from power-on-reset assertions raised during low-power operation.

    Why it matters

    Preserves state across low-power transitions, so aggressive power saving does not cost peripheral reliability.

All patents assigned to Texas Instruments Incorporated. Numbers link to the full specification on Google Patents. Three further applications are pending, with counterparts filed in Europe, China, Japan and under the PCT.